Controlling Germanium CMP Selectivity through Slurry Mediation by Surface Active Agents

New developments and device performance requirements in microelectronics industry add to the challenges in chemical mechanical planarization (CMP) process. One of the recently introduced materials to semiconductor manufacturing is germanium which enables improved device performance through better channel mobility in shallow trench isolation (STI) applications for advanced circuits. This paper focuses on controlling germanium/silica selectivity for advanced STI CMP applications through slurry modification by surface active agents. Surface adsorption characteristics of cationic and anionic surfactants on germanium and silica wafers are analyzed in order to control selectivity as well as the defectivity performance of the CMP applications. The effects of surfactant charge and concentration (up to self-assembly) are studied in terms of slurry stability, material removal rates and surface defectivity. Surface charge manipulation by the surfactant adsorption on the germanium surface is presented as the main criteria on the selection of the proper surfactant/oxidizer systems for CMP. The outlined correlations are systematically presented to highlight slurry modification criteria for the desired selectivity results. Consequently, the paper evaluates the slurry selectivity control and improvement criteria for the new materials introduced to microelectronics applications with CMP requirement by evaluating the germanium silica system as a model application.

Source:IOPscience

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Development, Optimization and Evaluation of a CF4 Pretreatment Process to Remove Unwanted Interfacial Layers in Stacks of CVD and PECVD Polycrystalline Silicon-Germanium for MEMS Applications

Poly-crystalline Silicon-Germanium is a promising structural material for post-processing Micro Electro-Mechanical Systems (MEMS) above CMOS due to its excellent mechanical and electrical properties when deposited at CMOS compatible temperatures. In this work we demonstrate a technique of removing unwanted interfacial (silicon-) germanium oxide layers that form on the surface of SiGe depositions as soon as the wafers are removed from the deposition chamber and exposed to an O2 ambient.

Source:IOPscience

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Lateral Gemanium Growth for Local GeOI Fabrication

High quality local Germanium-on-oxide (GeOI) wafers are fabricated using selective lateral germanium (Ge) growth technique by a single wafer reduced pressure chemical vapor deposition system. Mesa structures of 300 nm thick epitaxial silicon (Si) interposed by SiO2 cap and buried oxide are prepared. HCl vapor phase etching of Si is performed prior to selective Ge growth to remove a part of the epitaxial Si to form cavity under the mesa. By following selective Ge growth, the cavity was filled. Cross section TEM shows dislocations of Ge which are located near Si / Ge interface only. This mechanism is similar to aspect-ratio-trapping but here we are using a horizontal approach, which offers the option to remove the defective areas by standard structuring techniques. By plan view TEM it is shown, that the dislocations in Ge which direct to SiO2 cap or to buried-oxide (BOX) are located near the interface of Si and Ge. The dislocations which run parallel to BOX are observed only in [110] or equivalent direction. The resulting Ge grown toward [010] direction contains no dislocations. A root mean square of roughness of ~0.2 nm is obtained after the SiO2 cap removal. Tensile strain in the Ge layer is observed due to higher thermal expansion coefficient of Ge compared to Si and SiO2.

Source:IOPscience

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(Invited) Optoelectronic Monolithic Integration of Waveguided Metal-Germanium-Metal Photodetector and Ge CMOSFETs on SOI Wafer

We demonstrate monolithic integration of waveguided Metal- Germanium -Metal photodetector (WG-MGM-PD) and Ge CMOS with high-k dielectric and metal gate on SOI wafer using novel epi-growth technique. WG-MGM-PD achieves a responsivity of 0.6A/W and speed (f3dB) of 17.4GHz. Ge CMOS with ultra-thin EOT (1.4nm) was demonstrated with 2 times hole mobility improvement over the Si universal mobility and very low gate leakage current (10-5~10-4A/cm2).

Source:IOPscience

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Mesoporous Germanium Formation by Electrochemical Etching

Uniform thick mesoporous germanium layers are reproducibly formed on 4 in. p-type Ge wafers by electrochemical etching in highly concentrated HF electrolytes. Pore formation by anodic etching in germanium leads to a constant dissolution of the porous layer. The growth rate of the porous Ge layer is therefore given by the difference between the etch rate at the porous layer/substrate wafer interface and the dissolution rate at the electrolyte/porous layer interface. The growth rate lies in the range of 0.071–2.7 nm/min for etching current densities of , while both the etch rate and the dissolution rate lie in the range of several micrometers per minute. We define the substrate usage as the ratio of the growth rate and the etch rate. This substrate usage determines the growth efficiency of the porous layer and lies in the range of 0.2–2%. Thus, the substrate wafer is thinned substantially during anodic porous layer formation. Constantly alternating from an anodic to a cathodic bias prevents the thinning of the substrate. The dissolution rate decreases, and the usage increases up to 98%.

Source:IOPscience

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The Diffused Shot‐melting Technique for Making Germanium and Silicon p‐n Junction Devices

The diffused shot‐melting technique involves the melting and resolidifying of a piece (conveniently obtained in the form of shot) of semiconductor on a wafer of the same material (having essentially the same melting point) to form a single crystal boundary region, and the subsequent diffusion of impurities across the interface. Shot‐melting may be done so quickly that the interface coincides with the original surface of the wafer. Impurity contents of the shot and wafer may be chosen so that a variety of p‐n junction devices results after diffusion, and several junctions may be made on the same wafer by this process to form more complex structures. Although lifetime and resistivity changes generally occur, they can often be minimized by subsequent treatment such as alloy gettering or annealing. Simplicity and flexibility of diffused shot‐melting have made it a convenient laboratory technique for making many semiconductor devices.

Source:IOPscience

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Resist Stripping Process on Germanium : a Basic Post-Implant Study

Germanium and Germanium-On-Insulator (GeOI) MOSFETs with high-k gate dielectrics have received recent attention for the advanced technology nodes, because of the better carrier transport properties in Ge compared to Si. For Ge or GeOI CMOS, it is mandatory to determine Ge dedicated resist stripping processes, because of the Germanium non-compatibility with actual cleaning solutions. An initial compatibility study shows a passivation effect on germanium during dry step for high N2/ (O2+N2) plasma ratio. For the post active area etching, dry stripping performed on patterned Poly-Ge-On-Insulator (PolyGeOI) wafers shows good compatibility. The lateral Ge consumption due to the water rinse step is minimized by dry process, indicating a plasma passivation effect. Post implant stripping is especially difficult because the Si typical solutions are highly aggressive for Ge, and also because of the resist graphitization. Using a ramping temperature process, a good resist removal efficiency has been achieved.

Source:IOPscience

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Relationships of the Chemical and Electrical Interfacial Properties of Germanium ‐ SiO2 Systems

Germanium‐silicon dioxide structures were prepared by depositing on cleaned germanium wafers using chemical vapor deposition (CVD) from the silane‐oxygen reaction at 450°C. The structures were then annealed in various gas environments, Ar, , and a  and  forming gas, at 600°C for 2 hr. For samples annealed in forming gas, the interface state density measured by C‐V techniques shows a high density near the band edges (1014/cm2‐eV). For samples annealed in oxygen, it decreases to 1011/cm2‐eV. High surface recombination velocity was observed in the samples annealed in forming gas. The measured results of charge generation and injection indicated charge losses to the interface states but not to oxide traps, whose time constant for trapping is longer than the normal injection time . In order to understand the effects of annealing with different gas environments, profile analyses of the structures were carried out using secondary ion mass spectrometry (SIMS) and Auger electron spectroscopy (AES). For the samples annealed in oxygen, the presence of germanium oxide was identified by observing the low energy Auger spectrum at the interface in comparison with the spectrum obtained for a standard  sample. The profile of the germanium spectrum obtained using SIMS can be used to identify the presence of the oxide because of the enhanced secondary ion yield of the oxide. In the case of the forming gas anneal, the hydrogen appears to diffuse into the interface resulting in a high interface state density. The profile of hydrogen concentration for the structures was also obtained. It is concluded that the increase of the interface state density of a  system due to the forming gas anneal appears to result from dissolved hydrogen diffusing through the . The reduction of interface state density of the structure annealed in oxygen is probably due to the oxidation of germanium and dissolved hydrogen, which reduces the defects originally present in the interface region following the  deposition.

Source:IOPscience

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Advanced Characterization of a Direct Wafer Bonding-compatible Germanium Exfoliation Process

In this study, it is demonstrated that the propagation of long-range cracks in hydrogen-implanted germanium with a low-temperature exfoliation process (300 {degree sign}C max) is as complete as with conventional exfoliation processes that take place at higher temperatures. Such low-temperature exfoliation process is fully compliant with direct silicon to germanium wafer bonding. It allows for limited lattice deformation - enhanced bond strength i.e. - and limited voids formation at the bond interface during post-bonding anneal.

Source:IOPscience

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Fabrication of Relaxed Germanium on Insulator via Room Temperature Wafer Bonding

We report on the fabrication of, high quality, monocrystalline relaxed Germanium with ultra-low roughness on insulator (GeOI) using low-temperature direct wafer bonding. We observe that a two-step epitaxially grown germanium film fabricated on silicon by reduced pressure chemical vapor deposition can be directly bonded to a SiO2 layer using a thin Al2O3 as bonding mediator. After removing the donor substrate silicon the germanium layer exhibits a complete relaxation without degradation in crystalline quality and no stress in the film. . The results suggest that the fabricated high quality GeOI substrate is a suitable platform for high performance device applications.

Source:IOPscience

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(Invited) Germanium on Sapphire Technology

Silicon-on-sapphire (SOS) substrates have been proven to offer significant advantages in the integration of passive and active devices in RF circuits. Germanium on insulator technology is a candidate for future higher performance circuits. Thus the advantages of employing a low loss dielectric substrate other than a silicon-dioxide layer on silicon will be even greater. This paper covers the production of germanium on sapphire (GeOS) substrates by wafer bonding. The quality of the germanium back interface is studied and a tungsten self-aligned gate process MOST process has been developed. High low field mobilities of 450-500 cm2/V-s have been achieved for p-channel MOSTs produced on GeOS substrates. Thick germanium on alumina (GOAL) substrates have also been produced.

Source:IOPscience

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Hydrogen Implantation in Germanium

Hydrogen implantation of germanium is a promising technique for layer transfer. However, both the implantation process, and subsequent heat treatment can create defects in the transferred layer, which detrimentally effect the performance of devices fabricated on these transferred layers. In this study, implanted Germanium wafers were given various anneals and analysed optically and by spreading resistance, to gain insight on the nature of such defects. GeOI layers were produced by thermal splitting of implanted germanium wafers bonded to sapphire handle substrates.

Source:IOPscience

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The Study on Defects of Germanium-on-Insulator Fabricated by a Low Temperature Smart-Cut Process

Germanium-on-insulator (GeOI) was manufactured by a low temperature Smart-cut process. The blistering of H-implanted Ge wafer was first studied and the kinetics of blistering onset (time) as a function of annealing temperature was described to determine the subsequent splitting. Germanium layer transfer was achieved by a 2700C annealing after the atomic level Ge/SiO2 wafer bonding was formed by a 1500C annealing. The defects on the transferred Ge layer were mitigated thanks to the extended annealing and mainly distributed at the rim of GeOI wafer.

Source:IOPscience

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Gaseous Diffusion of Arsenic and Phosphorus into Germanium

Presence of germanium arsenide was found at the germanium surface, particularly at arsenic surface concentrations exceeding 1019 at./cc, using electron diffraction techniques. Thermal conversion of the interior of the germanium wafers (which were 15 ohm‐cm N‐type) to P‐type could be suppressed by arsenic surface concentrations exceeding 5.1018 at./cc. This elimination of thermal conversion depends on the surface to volume ratio of the wafer. It is proposed that the thermal conversion level in the bulk of the indiffused material depends on the electric field which arises during diffusion if the impurity concentration exceeds the intrinsic carrier concentration.

Source:IOPscience

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Germanium Back‐Side Gettering of Gold in Silicon

A novel back‐side gettering technique was developed. The technique consists of applying germanium to the back side of a silicon wafer and then annealing in either a nitrogen or an oxygen ambient. The concentration profiles for gold before and after anneals were established to better than the part per million (ppm) level by using atomic absorption spectroscopy. The minority carrier lifetime of control and gettered samples was determined. The technique was found to be effective for the removal of gold from the active device region of a silicon wafer. The difference in activity coefficients for gold in silicon and gold in germanium is the theoretical basis for the gettering of gold from the silicon to the germanium on the back side. In addition to gettering gold from the front surface of the wafer, comparison was made of a germanium‐gettered wafer with a control wafer, showing that the application of germanium to the back side of a silicon wafer, followed by thermal annealing, is effective in preventing the formation of oxidation‐induced stacking faults (OISF) during high temperature oxidation.

Source:IOPscience

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