Feb 25, 2020

Advanced Characterization of a Direct Wafer Bonding-compatible Germanium Exfoliation Process

In this study, it is demonstrated that the propagation of long-range cracks in hydrogen-implanted germanium with a low-temperature exfoliation process (300 {degree sign}C max) is as complete as with conventional exfoliation processes that take place at higher temperatures. Such low-temperature exfoliation process is fully compliant with direct silicon to germanium wafer bonding. It allows for limited lattice deformation - enhanced bond strength i.e. - and limited voids formation at the bond interface during post-bonding anneal.

Source:IOPscience

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Feb 19, 2020

Fabrication of Relaxed Germanium on Insulator via Room Temperature Wafer Bonding

We report on the fabrication of, high quality, monocrystalline relaxed Germanium with ultra-low roughness on insulator (GeOI) using low-temperature direct wafer bonding. We observe that a two-step epitaxially grown germanium film fabricated on silicon by reduced pressure chemical vapor deposition can be directly bonded to a SiO2 layer using a thin Al2Oas bonding mediator. After removing the donor substrate silicon the germanium layer exhibits a complete relaxation without degradation in crystalline quality and no stress in the film. . The results suggest that the fabricated high quality GeOI substrate is a suitable platform for high performance device applications.

Source:IOPscience

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Feb 11, 2020

(Invited) Germanium on Sapphire Technology

Silicon-on-sapphire (SOS) substrates have been proven to offer significant advantages in the integration of passive and active devices in RF circuits. Germanium on insulator technology is a candidate for future higher performance circuits. Thus the advantages of employing a low loss dielectric substrate other than a silicon-dioxide layer on silicon will be even greater. This paper covers the production of germanium on sapphire (GeOS) substrates by wafer bonding. The quality of the germanium back interface is studied and a tungsten self-aligned gate process MOST process has been developed. High low field mobilities of 450-500 cm2/V-s have been achieved for p-channel MOSTs produced on GeOS substrates. Thick germanium on alumina (GOAL) substrates have also been produced.

Source:IOPscience

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Jan 20, 2020

Hydrogen Implantation in Germanium

Hydrogen implantation of germanium is a promising technique for layer transfer. However, both the implantation process, and subsequent heat treatment can create defects in the transferred layer, which detrimentally effect the performance of devices fabricated on these transferred layers. In this study, implanted Germanium wafers were given various anneals and analysed optically and by spreading resistance, to gain insight on the nature of such defects. GeOI layers were produced by thermal splitting of implanted germanium wafers bonded to sapphire handle substrates.

Source:IOPscience

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Jan 13, 2020

The Study on Defects of Germanium-on-Insulator Fabricated by a Low Temperature Smart-Cut Process

Germanium-on-insulator (GeOI) was manufactured by a low temperature Smart-cut process. The blistering of H-implanted Ge wafer was first studied and the kinetics of blistering onset (time) as a function of annealing temperature was described to determine the subsequent splitting. Germanium layer transfer was achieved by a 2700C annealing after the atomic level Ge/SiO2 wafer bonding was formed by a 1500C annealing. The defects on the transferred Ge layer were mitigated thanks to the extended annealing and mainly distributed at the rim of GeOI wafer.

Source:IOPscience

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Jan 7, 2020

Gaseous Diffusion of Arsenic and Phosphorus into Germanium

Presence of germanium arsenide was found at the germanium surface, particularly at arsenic surface concentrations exceeding 1019 at./cc, using electron diffraction techniques. Thermal conversion of the interior of the germanium wafers (which were 15 ohm‐cm N‐type) to P‐type could be suppressed by arsenic surface concentrations exceeding 5.1018 at./cc. This elimination of thermal conversion depends on the surface to volume ratio of the wafer. It is proposed that the thermal conversion level in the bulk of the indiffused material depends on the electric field which arises during diffusion if the impurity concentration exceeds the intrinsic carrier concentration.

Source:IOPscience
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Jan 2, 2020

Germanium Back‐Side Gettering of Gold in Silicon

A novel back‐side gettering technique was developed. The technique consists of applying germanium to the back side of a silicon wafer and then annealing in either a nitrogen or an oxygen ambient. The concentration profiles for gold before and after anneals were established to better than the part per million (ppm) level by using atomic absorption spectroscopy. The minority carrier lifetime of control and gettered samples was determined. The technique was found to be effective for the removal of gold from the active device region of a silicon wafer. The difference in activity coefficients for gold in silicon and gold in germanium is the theoretical basis for the gettering of gold from the silicon to the germanium on the back side. In addition to gettering gold from the front surface of the wafer, comparison was made of a germanium‐gettered wafer with a control wafer, showing that the application of germanium to the back side of a silicon wafer, followed by thermal annealing, is effective in preventing the formation of oxidation‐induced stacking faults (OISF) during high temperature oxidation.

Source:IOPscience
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