A thin transition film formed by plasma exposure contributes to the germanium surface hydrophilicity*

Plasma treatment and 10% NH4OH solution rinsing were performed on a germanium (Ge) surface. It was found that the Ge surface hydrophilicity after O2 and Ar plasma exposure was stronger than that of samples subjected to N2 plasma exposure. This is because the thin GeO x film formed on Ge by O2 or Ar plasma is more hydrophilic than GeO x N y formed by N2 plasma treatment. A flat (RMS < 0:5 nm) Ge surface with high hydrophilicity (contact angle smaller than 3°) was achieved by O2 plasma treatment, showing its promising application in Ge low-temperature direct wafer bonding.

Source:IOPscience
For more information, please visit our website: www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Annealing Effects on Ge/SiO2 Interface Structure in Wafer-Bonded Germanium-on-Insulator Substrates

We have investigated annealing effects on Ge/SiO2 interfaces in wafer-bonded germanium-on-insulator substrates using transmission electron microscopy and electron energy loss spectroscopy. A number of nanometer-sized hollows were observed at the Ge/SiO2 interfaces after annealing at 500 and 600 °C, while the density of these hollows was very small after annealing at 700 and 800 °C. The hollows are attributed to the formation of amorphous oxides of Si-rich Si1-xGexO2. The mechanism for the formation and disappearance of these amorphous hollows on the Ge substrates is discussed.

Source:IOPscience
For more information, please visit our website: www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Electrical Characterization of Wafer-Bonded Germanium-on-Insulator Substrates Using a Four-Point-Probe Pseudo-Metal–Oxide–Semiconductor Field-Effect Transistor

The electrical characteristics of wafer-bonded non-doped germanium-on-insulator (GOI) substrates were investigated using a four-point-probe pseudo-metal–oxide–semiconductor field-effect transistor. Annealing the wafer-bonded GOI substrates in vacuum strongly influenced their electrical characteristics. GOI samples annealed at temperatures below 500 °C exhibited n-channel depletion transistor operation, whereas GOI samples annealed at temperatures between 550 and 600 °C exhibited p-channel depletion transistor operation. The carrier mobility strongly depended on the sweep direction of the gate voltage; this characteristic disappeared after annealing at temperatures above 550 °C. The dependence of the electrical characteristics on the annealing temperature is explained in terms of the influence of the defect states on energy band bending near the interface.


Source:IOPscience
For more information, please visit our website: www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Phonon Limited Electron Mobility in Germanium FinFETs: Fin Direction Dependence

We investigate the phonon limited electron mobility in germanium (Ge) fin field-effect transistors (FinFETs) with fin rotating within (001), (110), and (111)-oriented wafers. The coupled Schrödinger–Poisson equations are solved self-consistently to calculate the electronic structures for the two-dimensional electron gas, and Fermi's golden rule is used to calculate the phonon scattering rate. It is concluded that the intra-valley acoustic phonon scattering is the dominant mechanism limiting the electron mobility in Ge FinFETs. The phonon limited electron motilities are influenced by wafer orientation, channel direction, fin thickness W fin, and inversion charge density N inv. With the fixed W fin, fin directions of $\langle 110\rangle $, $\langle 1\bar{1}2\rangle $ and $\langle \bar{1}10\rangle $ within (001), (110), and (111)-oriented wafers provide the maximum values of electron mobility. The optimized Wfin for mobility is also dependent on wafer orientation and channel direction. As Ninv increases, phonon limited mobility degrades, which is attributed to electron repopulation from a higher mobility valley to a lower mobility valley as Ninv increases.

Source:IOPscience
For more information, please visit our website: www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com