Control wafer bow of InGaP on 200 mm Si by strain engineering

When epitaxially growing III–V compound semiconductors on Si substrates the mismatch of coefficients of thermal expansion (CTEs) between III–V and Si causes stress and wafer bow. The wafer bow is deleterious for some wafer-scale processing especially when the wafer size is large. Strain engineering was applied in the epitaxy of InGaP films on 200 mm silicon wafers having high quality germanium buffers. By applying compressive strain in the InGaP films to compensate the tensile strain induced by CTE mismatch, wafer bow was decreased from about 100 μm to less than 50 μm. X-ray diffraction studies show a clear trend between the decrease of wafer bow and the compensation of CTE mismatch induced tensile strain in the InGaP layers. In addition, the anisotropic strain relaxation in InGaP films resulted in anisotropic wafer bow along two perpendicular (110) directions. Etch pit density and plane-view transmission electron microscopy characterizations indicate that threading dislocation densities did not change significantly due to the lattice-mismatch applied in the InGaP films. This study shows that strain engineering is an effective method to control wafer bow when growing III–V semiconductors on large size Si substrates.

Source:IOPscience

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Charge trapping and reliability characteristics of sputtered Y2O3 high-k dielectrics on N- and S-passivated germanium

We demonstrate the potential of sulfur passivation to improve the interface characteristics between germanium (Ge) and Y2O3 high-k gate dielectric. Effects of nitrogen (N) and sulfur (S) passivation of the Ge surface on the charge trapping and reliability properties of Y2O3/Ge gate stacks are studied in detail and the results are compared. Sulfur passivation of the Ge surface has been performed using both the wet sulfidation technique with aqueous ammonium sulfide and plasma sulfidation with H2S gas. N-passivation of Ge substrates has been performed in NO plasma for comparison. Ultrathin (~15 nm) Y2O3 films are deposited on both the N- and S-passivated p-Ge (1 0 0) wafers. Y2O3 films on the S-passivated Ge surface show low fixed oxide charge and interface state density than what is achieved with N-passivation. The electrical characterization results of MOS capacitors with Y2O3films reveal the potential of S-passivation for the fabrication of Y2O3/Ge gate stacks for Ge MOSFETs.

Source:IOPscience

For more information, please visit our website: www.semiconductorwafers.net,

send us email at angel.ye@powerwaywafer.com or powerwaymaterial@gmail.com