The measured positive and negative magnetoresistance for n-type germanium at room temperature

Magnetoresistance (MR) for n-type germanium wafers by in-line-four-terminal method at room temperature are explored. Conspicuously, the variation of the measured MR as a function of applied current and voltage-terminal separation is observed. With a further increase of applied current, the measured MR initially increases, passes through a peak value at a certain current and then finally decreases. The measured MR increases with an increase of the value of voltage-terminal separation. The most important outcome of this study is the observation of negative MR for the smallest voltage-terminal separation of 2 µm, and the sign change of the measured MR can be achieved by magnetic fields. These interesting results may lead to an alternative approach to future magneto-electronic devices.

Source:IOPscience

For more information, please visit our website: www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Annealing Effects on Ge/SiO2 Interface Structure in Wafer-Bonded Germanium-on-Insulator Substrates

We have investigated annealing effects on Ge/SiO2 interfaces in wafer-bonded germanium-on-insulator substrates using transmission electron microscopy and electron energy loss spectroscopy. A number of nanometer-sized hollows were observed at the Ge/SiO2 interfaces after annealing at 500 and 600 °C, while the density of these hollows was very small after annealing at 700 and 800 °C. The hollows are attributed to the formation of amorphous oxides of Si-rich Si1-xGexO2. The mechanism for the formation and disappearance of these amorphous hollows on the Ge substrates is discussed.

Source:IOPscience

For more information, please visit our website: www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Thin film germanium on silicon created via ion implantation and oxide trapping

We present a novel process for integrating germanium with (SOI)  silicon-on-insulator wafers. Germanium is implanted into SOI which is then oxidized, trapping the germanium between the two oxide layers (the grown oxide and the buried oxide). With careful control of the implantation and oxidation conditions this process creates a thin layer (current experiments indicate up to 20-30nm) of almost pure germanium. The layer can be used potentially for fabrication of integrated photo-detectors sensitive to infrared wavelengths, or may serve as a seed for further germanium growth. Results are presented from electron microscopy and Rutherford back-scattering analysis, as well as preliminary modelling using an analytical description of the process.

Source:IOPscience

For more information, please visit our website: www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Fabrication of Ge-on-insulator wafers by Smart-CutTM with thermal management for undamaged donor Ge wafers

Newly engineered substrates consisting of semiconductor-on-insulator are gaining much attention as starting materials for the subsequent transfer of semiconductor nanomembranes via selective etching of the insulating layer. Germanium-on-insulator (GeOI) substrates are critically important because of the versatile applications of Ge nanomembranes (Ge NMs) toward electronic and optoelectronic devices. Among various fabrication techniques, the Smart-CutTM technique is more attractive than other methods because a high temperature annealing process can be avoided. Another advantage of Smart-CutTM is the reusability of the donor Ge wafer. However, it is very difficult to realize an undamaged Ge wafer because there exists a large mismatch in the coefficient of thermal expansion among the layers. Although an undamaged donor Ge wafer is a prerequisite for its reuse, research related to this issue has not yet been reported. Here we report the fabrication of 4-inch GeOI substrates using the direct wafer bonding and Smart-CutTM process with a low thermal budget. In addition, a thermo-mechanical simulation of GeOI was performed by COMSOL to analyze induced thermal stress in each layer of GeOI. Crack-free donor Ge wafers were obtained by annealing at 250 °C for 10 h. Raman spectroscopy and x-ray diffraction (XRD) indicated similarly favorable crystalline quality of the Ge layer in GeOI compared to that of bulk Ge. In addition, Ge p-n diodes using transferred Ge NM indicate a clear rectifying behavior with an on and off current ratio of 500 at ±1 V. This demonstration offers great promise for high performance transferrable Ge NM-based device applications.

Source:IOPscience

For more information, please visit our website: www.semiconductorwafers.net,
send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com