tag:blogger.com,1999:blog-67930361424508993022023-11-15T23:40:57.840-08:00Germanium WafersPWAM offers semiconductor materials,Ge(Germanium) Single Crystals and Wafers grown by VGF / LECwafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.comBlogger144125tag:blogger.com,1999:blog-6793036142450899302.post-3567937967196457512020-04-19T20:37:00.006-07:002020-04-19T20:37:54.566-07:00Controlling Germanium CMP Selectivity through Slurry Mediation by Surface Active Agents<span style="color: #333333;"><span style="font-family: Arial, Helvetica, sans-serif;">New developments <b>and device</b> performance requirements in microelectronics industry add to the challenges in chemical mechanical planarization (CMP) process. One of the recently introduced materials to semiconductor manufacturing is <b>germanium</b> which enables improved device performance through better channel mobility in shallow trench isolation (STI) applications for advanced circuits. This paper focuses on controlling germanium/silica selectivity for advanced STI CMP applications through slurry modification by surface active agents. Surface adsorption characteristics of cationic and anionic surfactants on germanium and silica wafers are analyzed in order to control selectivity as well as the defectivity performance of the <b>CMP</b> applications. The effects of surfactant charge and concentration (up to self-assembly) are studied in terms of slurry stability, material removal rates and surface defectivity. Surface charge manipulation by the surfactant adsorption on the germanium surface is presented as the main criteria on the selection of the proper surfactant/oxidizer systems for CMP. The outlined correlations are systematically presented to highlight slurry modification criteria for the desired selectivity results. Consequently, the paper evaluates the slurry selectivity control and improvement criteria for the new materials introduced to microelectronics applications with CMP requirement by evaluating the germanium silica system as a model application.</span></span><br />
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<span style="font-size: x-small;"><span style="background-color: white; color: #222222; font-family: Arial, Helvetica, sans-serif;"><span style="text-align: justify;">Source:IOPscience</span></span></span><br />
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wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-36274374956060231562020-04-12T20:48:00.005-07:002020-04-12T20:48:58.038-07:00Development, Optimization and Evaluation of a CF4 Pretreatment Process to Remove Unwanted Interfacial Layers in Stacks of CVD and PECVD Polycrystalline Silicon-Germanium for MEMS Applications<span style="color: #333333;"><span style="font-family: Arial, Helvetica, sans-serif;">Poly-crystalline Silicon-<b>Germanium</b> is a promising <b>structural material</b> for post-processing Micro Electro-Mechanical Systems (MEMS) above CMOS due to its excellent mechanical and electrical properties when deposited at CMOS compatible temperatures. In this work we demonstrate a technique of removing unwanted interfacial (silicon-) <b>germanium oxide</b> layers that form on the surface of SiGe depositions as soon as the wafers are removed from the deposition chamber and exposed to an O2 ambient.</span></span><br />
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wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-15351947761362383802020-04-06T19:10:00.001-07:002020-04-06T19:10:13.505-07:00Lateral Gemanium Growth for Local GeOI Fabrication<span style="font-family: Arial, Helvetica, sans-serif;"><span style="color: #333333;">High quality local Germanium-on-oxide (GeOI) wafers are fabricated using selective lateral<b> germanium</b> (Ge) growth technique by a single wafer reduced pressure chemical vapor deposition system. Mesa structures of 300 nm thick epitaxial silicon (Si) interposed by <b>SiO</b></span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;"><b>2</b></span><span style="color: #333333;"> cap and buried oxide are prepared. HCl vapor phase etching of Si is performed prior to selective Ge growth to remove a part of the epitaxial Si to form cavity under the mesa. By following selective Ge growth, the cavity was filled. Cross section TEM shows dislocations of Ge which are located near Si / Ge interface only. This mechanism is similar to aspect-ratio-trapping but here we are using a horizontal approach, which offers the option to remove the defective areas by standard structuring techniques. By plan view TEM it is shown, that the dislocations in Ge which direct to SiO</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;"> cap or to buried-oxide (BOX) are located near the interface of Si and Ge. The dislocations which run parallel to BOX are observed only in [110] or equivalent direction. The resulting Ge grown toward [010] direction contains no dislocations. A root mean square of roughness of ~0.2 nm is obtained after the SiO</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;"> cap removal. Tensile strain in the Ge layer is observed due to higher thermal expansion coefficient of Ge compared to Si and SiO</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;">.</span></span><br />
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<span style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;"><span style="background-color: white; color: #222222;"><span style="text-align: justify;">Source:IOPscience</span></span></span><br />
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wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-13843646420117209032020-03-29T19:23:00.001-07:002020-03-29T19:23:20.438-07:00(Invited) Optoelectronic Monolithic Integration of Waveguided Metal-Germanium-Metal Photodetector and Ge CMOSFETs on SOI Wafer<span style="color: #333333;"><span style="font-family: Arial, Helvetica, sans-serif;">We demonstrate monolithic integration of waveguided Metal- Germanium -Metal <b>photodetector</b> (WG-MGM-PD) and Ge CMOS with high-k dielectric and metal gate on SOI wafer using novel epi-growth technique. WG-MGM-PD achieves a responsivity of 0.6A/W and speed (f3dB) of 17.4GHz. Ge CMOS with ultra-thin <b>EOT</b> (1.4nm) was demonstrated with 2 times hole mobility improvement over the Si universal mobility and very low <b>gate leakage current </b>(10-5~10-4A/cm2).</span></span><br />
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wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-32358993178881585962020-03-23T00:47:00.000-07:002020-03-23T00:47:06.161-07:00Mesoporous Germanium Formation by Electrochemical Etching<span style="color: #333333; font-family: minion-pro, Georgia, "Times New Roman", STIXGeneral, serif;">Uniform thick mesoporous germanium layers are reproducibly formed on 4 in. p-type Ge wafers by <b>electrochemical etching</b> in highly concentrated HF electrolytes. Pore formation by anodic etching in germanium leads to a constant dissolution of the porous layer. The growth rate of the porous Ge layer is therefore given by the difference between the etch rate at the porous layer/substrate wafer interface and the dissolution rate at the electrolyte/porous layer interface. The growth rate lies in the range of 0.071–2.7 nm/min for etching current densities of </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/156/8/D310/jes_156_8_D310ieqn1.jpg" src="https://cdn.iopscience.com/images/1945-7111/156/8/D310/jes_156_8_D310ieqn1.jpg" style="border: 0px; color: #333333; font-family: minion-pro, Georgia, "Times New Roman", STIXGeneral, serif; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333; font-family: minion-pro, Georgia, "Times New Roman", STIXGeneral, serif;">, while both the etch rate and the <b>dissolution rate</b> lie in the range of several micrometers per minute. We define the substrate usage as the ratio of the growth rate and the etch rate. This substrate usage determines the <b>growth efficiency </b>of the porous layer and lies in the range of 0.2–2%. Thus, the substrate wafer is thinned substantially during anodic porous layer formation. Constantly alternating from an anodic to a cathodic bias prevents the thinning of the substrate. The dissolution rate decreases, and the usage increases up to 98%.</span><br />
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<span style="font-size: x-small;"><span style="background-color: white; color: #222222; font-family: Arial, Helvetica, sans-serif;"><span style="text-align: justify;">Source:IOPscience</span></span></span><br />
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wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-39802556376676547022020-03-17T18:54:00.003-07:002020-03-20T00:02:37.458-07:00The Diffused Shot‐melting Technique for Making Germanium and Silicon p‐n Junction Devices<span style="color: #333333;"><span style="font-family: "arial" , "helvetica" , sans-serif;">The diffused shot‐melting technique involves the melting and resolidifying of a piece (conveniently obtained in the form of shot) of semiconductor on a wafer of the same material (having essentially the same <b>melting point</b>) to form a <b>single crystal</b> boundary region, and the subsequent diffusion of impurities across the interface. Shot‐melting may be done so quickly that the interface coincides with the original surface of the wafer. Impurity contents of the shot and wafer may be chosen so that a variety of p‐n junction devices results after diffusion, and several junctions may be made on the same wafer by this process to form more complex structures. Although lifetime and resistivity changes generally occur, they can often be minimized by subsequent treatment such as alloy gettering or annealing. Simplicity and flexibility of diffused shot‐melting have made it a convenient laboratory technique for making many <b>semiconductor</b> devices.</span></span><br />
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wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-13807912129248153662020-03-10T19:06:00.004-07:002020-03-20T00:03:12.264-07:00Resist Stripping Process on Germanium : a Basic Post-Implant Study<span style="color: #333333;"><span style="font-family: "arial" , "helvetica" , sans-serif;">Germanium and <b>Germanium</b>-On-Insulator (GeOI) MOSFETs with high-k gate dielectrics have received recent attention for the advanced technology nodes, because of the better <b>carrier transport</b> properties in Ge compared to Si. For Ge or GeOI CMOS, it is mandatory to determine Ge dedicated resist stripping processes, because of the Germanium non-compatibility with actual cleaning solutions. An initial compatibility study shows a passivation effect on germanium during dry step for high N2/ (O2+N2) plasma ratio. For the post active area etching, dry stripping performed on patterned Poly-Ge-On-Insulator (PolyGeOI) wafers shows good compatibility. The lateral Ge consumption due to the water rinse step is minimized by <b>dry process</b>, indicating a plasma passivation effect. Post implant stripping is especially difficult because the Si typical solutions are highly aggressive for Ge, and also because of the resist graphitization. Using a ramping temperature process, a good resist removal efficiency has been achieved.</span></span><br />
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wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-55804367622987332822020-03-04T23:37:00.001-08:002020-03-20T00:03:35.928-07:00Relationships of the Chemical and Electrical Interfacial Properties of Germanium ‐ SiO2 Systems<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="color: #333333;"><b>Germanium</b>‐<b>silicon dioxide</b> structures were prepared by depositing </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/123/9/1392/jes_123_9_1392ieqn1.jpg" src="https://static.iopscience.com/2.26.1/img/lazy-loading-placeholder.gif" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;">on cleaned germanium wafers using<b> chemical vapor deposition</b> (CVD) from the silane‐oxygen reaction at 450°C. The structures were then annealed in various gas environments, Ar, </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/123/9/1392/jes_123_9_1392ieqn2.jpg" src="https://static.iopscience.com/2.26.1/img/lazy-loading-placeholder.gif" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;">, and a </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/123/9/1392/jes_123_9_1392ieqn3.jpg" src="https://static.iopscience.com/2.26.1/img/lazy-loading-placeholder.gif" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> and </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/123/9/1392/jes_123_9_1392ieqn4.jpg" src="https://static.iopscience.com/2.26.1/img/lazy-loading-placeholder.gif" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> forming gas, at 600°C for 2 hr. For samples annealed in forming gas, the interface state density measured by C‐V techniques shows a high density near the band edges (10</span><span style="border: 0px; bottom: 1ex; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; vertical-align: baseline;">14</span><span style="color: #333333;">/cm</span><span style="border: 0px; bottom: 1ex; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; vertical-align: baseline;">2</span><span style="color: #333333;">‐eV). For samples annealed in oxygen, it decreases to 10</span><span style="border: 0px; bottom: 1ex; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; vertical-align: baseline;">11</span><span style="color: #333333;">/cm</span><span style="border: 0px; bottom: 1ex; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; vertical-align: baseline;">2</span><span style="color: #333333;">‐eV. High surface recombination velocity was observed in the samples annealed in <b>forming gas</b>. The measured results of charge generation and injection indicated charge losses to the interface states but not to oxide traps, whose time constant for trapping is longer than the normal injection time </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/123/9/1392/jes_123_9_1392ieqn5.jpg" src="https://static.iopscience.com/2.26.1/img/lazy-loading-placeholder.gif" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;">. In order to understand the effects of annealing with different gas environments, profile analyses of the structures were carried out using secondary ion mass spectrometry (SIMS) and Auger electron spectroscopy (AES). For the samples annealed in oxygen, the presence of germanium oxide was identified by observing the low energy Auger spectrum at the interface in comparison with the spectrum obtained for a standard </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/123/9/1392/jes_123_9_1392ieqn6.jpg" src="https://static.iopscience.com/2.26.1/img/lazy-loading-placeholder.gif" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> sample. The profile of the germanium spectrum obtained using SIMS can be used to identify the presence of the oxide because of the enhanced secondary ion yield of the oxide. In the case of the forming gas anneal, the hydrogen appears to diffuse into the interface resulting in a high interface state density. The profile of hydrogen concentration for the structures was also obtained. It is concluded that the increase of the interface state density of a </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/123/9/1392/jes_123_9_1392ieqn7.jpg" src="https://static.iopscience.com/2.26.1/img/lazy-loading-placeholder.gif" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> system due to the forming gas anneal appears to result from dissolved hydrogen diffusing through the </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/123/9/1392/jes_123_9_1392ieqn8.jpg" src="https://static.iopscience.com/2.26.1/img/lazy-loading-placeholder.gif" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;">. The reduction of interface state density of the structure annealed in oxygen is probably due to the oxidation of germanium and dissolved hydrogen, which reduces the defects originally present in the interface region following the </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/123/9/1392/jes_123_9_1392ieqn9.jpg" src="https://static.iopscience.com/2.26.1/img/lazy-loading-placeholder.gif" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> deposition.</span></span><br />
<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="color: #333333;"><br /></span></span><span style="font-size: x-small;"><span style="background-color: white; color: #222222; font-family: "arial" , "tahoma" , "helvetica" , "freesans" , sans-serif;"><span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="text-align: justify;">Source:IOPscience</span></span></span></span><br />
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wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-79099568685282052892020-02-25T18:13:00.002-08:002020-03-20T00:03:51.044-07:00Advanced Characterization of a Direct Wafer Bonding-compatible Germanium Exfoliation Process<span style="color: #333333;"><span style="font-family: "arial" , "helvetica" , sans-serif;">In this study, it is demonstrated that the propagation of long-range cracks in hydrogen-implanted <b>germanium</b> with a low-temperature exfoliation process (300 {degree sign}C max) is as complete as with conventional exfoliation processes that take place at higher temperatures. Such low-temperature exfoliation process is fully compliant with direct silicon to germanium <b>wafer</b> bonding. It allows for limited lattice deformation - enhanced bond strength i.e. - and limited voids formation at the bond interface during post-bonding anneal.</span></span><br />
<span style="color: #333333;"><span style="font-family: "arial" , "helvetica" , sans-serif;"><br /></span></span><span style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;"><span style="background-color: white; color: #222222;"><span style="text-align: justify;">Source:IOPscience</span></span></span><br />
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wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-70878869420149772682020-02-19T01:10:00.003-08:002020-03-20T00:04:05.192-07:00Fabrication of Relaxed Germanium on Insulator via Room Temperature Wafer Bonding<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="color: #333333;">We report on the fabrication of, high quality, <b>monocrystalline</b> relaxed Germanium with ultra-low roughness on insulator (GeOI) using low-temperature direct wafer bonding. We observe that a two-step epitaxially grown <b>germanium</b> film fabricated on silicon by reduced pressure chemical vapor deposition can be directly bonded to a <b>SiO</b></span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;"><b>2</b></span><span style="color: #333333;"> layer using a thin Al</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;">O</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">3 </span><span style="color: #333333;">as bonding mediator. After removing the donor substrate silicon the germanium layer exhibits a complete relaxation without degradation in crystalline quality and no stress in the film. . The results suggest that the fabricated high quality GeOI substrate is a suitable platform for high performance device applications.</span></span><br />
<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="color: #333333;"><br /></span></span><span style="font-size: x-small;"><span style="background-color: white; color: #222222; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif;"><span style="font-family: Arial, Helvetica, sans-serif;"><span style="text-align: justify;">Source:IOPscience</span></span></span></span><br />
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wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-54724267072981031132020-02-11T23:41:00.004-08:002020-03-20T00:04:38.070-07:00(Invited) Germanium on Sapphire Technology<span style="color: #333333;"><span style="font-family: "arial" , "helvetica" , sans-serif;">Silicon-on-sapphire (SOS) substrates have been proven to offer significant advantages in the integration of passive and active devices in RF circuits. Germanium on insulator technology is a candidate for future higher performance circuits. Thus the advantages of employing a low loss dielectric substrate other than a silicon-dioxide layer on silicon will be even greater. This paper covers the production of germanium on sapphire (GeOS) substrates by wafer bonding. The quality of the germanium back interface is studied and a tungsten self-aligned gate process MOST process has been developed. High low field mobilities of 450-500 cm2/V-s have been achieved for p-channel MOSTs produced on GeOS substrates. Thick <b>germanium</b> on alumina (GOAL) substrates have also been produced.</span></span><br />
<span style="color: #333333;"><span style="font-family: "arial" , "helvetica" , sans-serif;"><br /></span></span><span style="font-size: x-small;"><span style="background-color: white; color: #222222; font-family: "arial" , "tahoma" , "helvetica" , "freesans" , sans-serif;"><span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="text-align: justify;">Source:IOPscience</span></span></span></span><br />
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wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-73255374114237824882020-01-20T19:36:00.002-08:002020-03-20T00:04:47.059-07:00Hydrogen Implantation in Germanium<span style="color: #333333;"><span style="font-family: "arial" , "helvetica" , sans-serif;">Hydrogen implantation of <b>germanium</b> is a promising technique for layer transfer. However, both the implantation process, and subsequent heat treatment can create defects in the transferred layer, which detrimentally effect the performance of devices fabricated on these transferred layers. In this study, implanted Germanium wafers were given various anneals and analysed optically and by spreading resistance, to gain insight on the nature of such defects. GeOI layers were produced by thermal splitting of implanted germanium wafers bonded to sapphire handle substrates.</span></span><br />
<span style="background-color: white; color: #333333; font-family: "arial" , "helvetica" , sans-serif; font-size: x-small;"><br /></span><span style="font-size: x-small;"><span style="background-color: white; color: #222222; font-family: "arial" , "tahoma" , "helvetica" , "freesans" , sans-serif;"><span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="text-align: justify;">Source:IOPscience</span></span></span></span><br />
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wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-78181976966511372112020-01-13T18:46:00.001-08:002020-03-20T00:04:59.929-07:00The Study on Defects of Germanium-on-Insulator Fabricated by a Low Temperature Smart-Cut Process<span style="color: #333333;"><span style="font-family: "arial" , "helvetica" , sans-serif;"><b>Germanium</b>-on-insulator (GeOI) was manufactured by a low temperature Smart-cut process. The blistering of H-implanted Ge wafer was first studied and the kinetics of blistering onset (time) as a function of annealing temperature was described to determine the subsequent splitting. Germanium layer transfer was achieved by a 2700C annealing after the atomic level Ge/SiO2 wafer bonding was formed by a 1500C annealing. The defects on the transferred Ge layer were mitigated thanks to the extended annealing and mainly distributed at the rim of GeOI <b>wafer.</b></span></span><br />
<span style="color: #333333;"><span style="font-family: "arial" , "helvetica" , sans-serif;"><b><br /></b></span></span><span style="font-size: x-small;"><span style="background-color: white; color: #222222; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif;"><span style="font-family: Arial, Helvetica, sans-serif;"><span style="text-align: justify;">Source:IOPscience</span></span></span></span><br />
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wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-91505202825859586142020-01-07T17:01:00.000-08:002020-01-07T17:01:02.399-08:00Gaseous Diffusion of Arsenic and Phosphorus into Germanium<span style="font-family: Arial, Helvetica, sans-serif;"><span style="color: #333333;">Presence of <b>germanium</b> arsenide was found at the germanium surface, particularly at arsenic surface concentrations exceeding 10</span><span style="border: 0px; bottom: 1ex; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; vertical-align: baseline;">19</span><span style="color: #333333;"> at./cc, using electron diffraction techniques. Thermal conversion of the interior of the germanium wafers (which were 15 ohm‐cm N‐type) to P‐type could be suppressed by arsenic surface concentrations exceeding 5.10</span><span style="border: 0px; bottom: 1ex; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; vertical-align: baseline;">18</span><span style="color: #333333;"> at./cc. This elimination of thermal conversion depends on the surface to volume ratio of the wafer. It is proposed that the thermal conversion level in the bulk of the indiffused material depends on the electric field which arises during diffusion if the impurity concentration exceeds the intrinsic carrier concentration.</span></span><br />
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<span style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;">Source:IOPscience</span></div>
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wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-58206141170006612062020-01-02T19:51:00.000-08:002020-01-02T19:51:10.539-08:00Germanium Back‐Side Gettering of Gold in Silicon<span style="color: #333333;"><span style="font-family: Arial, Helvetica, sans-serif;">A novel back‐side gettering technique was developed. The technique consists of applying <b>germanium</b> to the back side of a silicon wafer and then annealing in either a nitrogen or an oxygen ambient. The concentration profiles for gold before and after anneals were established to better than the part per million (ppm) level by using atomic absorption spectroscopy. The minority carrier lifetime of control and gettered samples was determined. The technique was found to be effective for the removal of gold from the active device region of a silicon wafer. The difference in activity coefficients for gold in silicon and gold in germanium is the theoretical basis for the gettering of gold from the silicon to the germanium on the back side. In addition to gettering gold from the front surface of the wafer, comparison was made of a germanium‐gettered wafer with a control wafer, showing that the application of germanium to the back side of a silicon wafer, followed by thermal annealing, is effective in preventing the formation of oxidation‐induced stacking faults (OISF) during high temperature oxidation.</span></span><br />
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<span style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;">Source:IOPscience</span></div>
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<span style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;">For more information, please visit our website: <a href="http://www.semiconductorwafers.net%2C/" style="color: #888888; text-decoration-line: none;">www.semiconductorwafers.net,</a><br style="color: #222222;" />send us email at <a href="mailto:sales@powerwaywafer.com" style="color: #333333; text-decoration-line: none;">sales@powerwaywafer.com</a> and <a href="mailto:powerwaymaterial@gmail.com" style="color: #333333; text-decoration-line: none;">powerwaymaterial@gmail.com</a></span></div>
wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-23283011223864268392019-12-25T00:00:00.002-08:002019-12-25T00:00:12.428-08:00The Stabilization of Germanium Surfaces by Ethylation: II . Chemical Analysis<span style="color: #333333;"><span style="font-family: Arial, Helvetica, sans-serif;">Radiotracer techniques and mass spectrometry have been employed in analyzing ethylated germanium surfaces; the results from these two analytical techniques are in good agreement. The number of ethyl fragments on a treated (111) germanium surface is the same as the number of surface <b>germanium </b>atoms, within experimental error. The surfaces are stable at temperatures below 200°C in vacuum and in air, but begin evolving C1 and C2 fragments above 200°C. At higher temperatures, additional hydrocarbon fragments are seen mass spectrometrically. Using wafers having labelled ethyl groups, it has been found that the treated surfaces are stable to immersion in common chemical solvents.</span></span><br />
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<span style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;">Source:IOPscience</span></div>
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<span style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;">For more information, please visit our website: <a href="http://www.semiconductorwafers.net%2C/" style="color: #888888; text-decoration-line: none;">www.semiconductorwafers.net,</a><br style="color: #222222;" />send us email at <a href="mailto:sales@powerwaywafer.com" style="color: #333333; text-decoration-line: none;">sales@powerwaywafer.com</a> and <a href="mailto:powerwaymaterial@gmail.com" style="color: #333333; text-decoration-line: none;">powerwaymaterial@gmail.com</a></span></div>
wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-6106526435980168152019-12-17T18:06:00.003-08:002019-12-17T18:06:37.643-08:00Heterostructures of germanium nanowires and germanium–silicon oxide nanotubes and growth mechanisms<span style="font-family: Arial, Helvetica, sans-serif;"><span style="color: #333333;">We report on a method to fabricate one-dimensional heterostructures of germanium nanowires (GeNWs) and <b>germanium</b>–<b>silicon oxide</b> nanotubes (GeSiO</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;"><i style="border: 0px; font-stretch: inherit; font-variant: inherit; font-weight: inherit; line-height: inherit; margin: 0px; padding: 0px; vertical-align: baseline;">x</i></span><span style="color: #333333;">NTs). The synthesis of the wire–tube heterostructures is carried out using a simple furnace set-up with germanium tetraiodide and germanium powders as growth precursors, gold-dotted silicon wafers as substrates and by controlling the temperature ramp rate/sequence of the growth precursors. Two types of wire–tube heterostructures resulting from distinct growth mechanisms are obtained. The type-1 heterostructure consists of a GeNW, grown via a gold-catalyzed vapour–liquid–solid process, at the lower end and a GeSiO</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;"><i style="border: 0px; font-stretch: inherit; font-variant: inherit; font-weight: inherit; line-height: inherit; margin: 0px; padding: 0px; vertical-align: baseline;">x</i></span><span style="color: #333333;">NT at the upper end. In contrast, the type-2 heterostructure is made up of a solid wire at the upper end and a hollow tube at the lower end. The solid wire portion of the type-2 heterostructure is formed through an oxide-assisted growth process.</span></span><br />
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<span style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;">Source:IOPscience</span></div>
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<span style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;">For more information, please visit our website: <a href="http://www.semiconductorwafers.net%2C/" style="color: #888888; text-decoration-line: none;">www.semiconductorwafers.net,</a><br style="color: #222222;" />send us email at <a href="mailto:sales@powerwaywafer.com" style="color: #333333; text-decoration-line: none;">sales@powerwaywafer.com</a> and <a href="mailto:powerwaymaterial@gmail.com" style="color: #333333; text-decoration-line: none;">powerwaymaterial@gmail.com</a></span></div>
wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-14032444600889148192019-12-11T18:22:00.005-08:002019-12-11T18:22:53.842-08:00Silicon and germanium nanostructures formed by spark discharge plasma<span style="color: #333333;"><span style="font-family: Arial, Helvetica, sans-serif;">Formation of semiconductor nanostructures on the surface of single crystalline silicon and <b>germanium</b> wafers by spark discharge plasma in air was investigated. The prepared nanostructures were analyzed by means of the scanning and transmission electron microscopy and optical spectroscopy of the photoluminescence and Raman scattering. The formed nanostructures exhibit a fractal-like morphology with interconnected nanocrystals of 2-200 nm sizes that is explained by repeated processes of spark ablation and subsequent condensation. While the size and morphology of the nanostructure depend on power sources of the spark discharge, short interaction times of spark discharge plasma and target determine a relatively <b>low efficiency</b> of the chemical oxidation of germanium and silicon, as well as low ionic temperatures of the plasma.</span></span><br />
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<span style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;">Source:IOPscience</span></div>
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<span style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;">For more information, please visit our website: <a href="http://www.semiconductorwafers.net%2C/" style="color: #888888; text-decoration-line: none;">www.semiconductorwafers.net,</a><br style="color: #222222;" />send us email at <a href="mailto:sales@powerwaywafer.com" style="color: #333333; text-decoration-line: none;">sales@powerwaywafer.com</a> and <a href="mailto:powerwaymaterial@gmail.com" style="color: #333333; text-decoration-line: none;">powerwaymaterial@gmail.com</a></span></div>
wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-27840528142443852052019-12-04T18:39:00.001-08:002019-12-04T18:39:05.225-08:00Selective Lateral Germanium Growth for Local GeOI Fabrication<div class="article-text wd-jnl-art-abstract cf" itemprop="description" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; line-height: 1.5; margin: 0px; padding: 0px; vertical-align: baseline;">
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<span style="font-family: Arial, Helvetica, sans-serif;"><span style="font-weight: inherit;">High quality local </span><b>Germanium</b><span style="font-weight: inherit;">-on-oxide (GeOI) wafers are fabricated using selective lateral germanium (Ge) growth technique by a single wafer reduced pressure chemical vapor deposition system. Mesa structures of 300 nm thick epitaxial silicon (Si) interposed by SiO</span><span style="border: 0px; font-stretch: inherit; font-style: inherit; font-variant: inherit; font-weight: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="font-weight: inherit;"> cap and buried oxide are prepared. HCl </span><b>vapor phase </b><span style="font-weight: inherit;">etching of Si is performed prior to selective Ge growth to remove a part of the epitaxial Si to form cavity under the mesa. By following selective Ge growth, the cavity was filled. Cross section TEM shows dislocations of Ge which are located near Si / Ge interface only. By plan view TEM, it is shown that the dislocations in Ge which direct to SiO</span><span style="border: 0px; font-stretch: inherit; font-style: inherit; font-variant: inherit; font-weight: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="font-weight: inherit;"> cap or to buried-oxide (BOX) are located near the interface of Si and Ge. The dislocations which run parallel to BOX are observed only in [110] and [1–10] direction resulting Ge grown toward [010] direction contains no dislocations. This mechanism is similar to aspect-ratio-trapping but here we are using a horizontal approach, which offers the option to remove the defective areas by standard structuring techniques. A root mean square of roughness of ~0.2 nm is obtained after the SiO</span><span style="border: 0px; font-stretch: inherit; font-style: inherit; font-variant: inherit; font-weight: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="font-weight: inherit;"> cap removal. Tensile strain in the Ge layer is observed due to higher thermal expansion coefficient of Ge compared to Si and SiO</span><span style="border: 0px; font-stretch: inherit; font-style: inherit; font-variant: inherit; font-weight: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="font-weight: inherit;">.</span></span></div>
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<span style="background-color: white;"><span style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;">Source:IOPscience</span></span></div>
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<span style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;"><span style="background-color: white;">For more information, please visit our website: <a href="http://www.semiconductorwafers.net%2C/" style="color: #888888; text-decoration-line: none;">www.semiconductorwafers.net,</a></span><br style="background-color: white; color: #222222;" /><span style="background-color: white;">send us email at </span><a href="mailto:sales@powerwaywafer.com" style="background-color: white; color: #333333; text-decoration-line: none;">sales@powerwaywafer.com</a><span style="background-color: white;"> and </span><a href="mailto:powerwaymaterial@gmail.com" style="background-color: white; color: #333333; text-decoration-line: none;">powerwaymaterial@gmail.com</a></span></div>
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wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-90445645313394745302019-11-27T18:46:00.002-08:002019-11-27T18:46:15.243-08:00A thin transition film formed by plasma exposure contributes to the germanium surface hydrophilicity*<span style="font-family: Arial, Helvetica, sans-serif;">Plasma treatment and 10% NH4OH solution rinsing were performed on a <b>germanium</b> (Ge) surface. It was found that the Ge surface hydrophilicity after O2 and Ar plasma exposure was stronger than that of samples subjected to N2 plasma exposure. This is because the thin GeO x film formed on Ge by O2 or Ar plasma is more hydrophilic than GeO x N y formed by N2 plasma treatment. A flat (RMS < 0:5 nm) Ge surface with high hydrophilicity (<b>contact angle</b> smaller than 3°) was achieved by O2 plasma treatment, showing its promising application in Ge low-temperature direct wafer bonding.</span><br />
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<span style="background-color: white; color: #333333; font-family: arial, helvetica, sans-serif; font-size: xx-small;">Source:IOPscience</span><br style="background-color: white; color: #222222; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 13.2px;" /><span style="background-color: white; color: #333333; font-family: arial, helvetica, sans-serif; font-size: xx-small;">For more information, please visit our website: <a href="http://www.semiconductorwafers.net%2C/" style="color: #888888; text-decoration-line: none;">www.semiconductorwafers.net,</a></span><br style="background-color: white; color: #222222; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 13.2px;" /><span style="background-color: white; color: #333333; font-family: arial, helvetica, sans-serif; font-size: xx-small;">send us email at </span><a href="mailto:sales@powerwaywafer.com" style="background-color: white; color: #333333; font-family: arial, helvetica, sans-serif; font-size: small; text-decoration-line: none;">sales@powerwaywafer.com</a><span style="background-color: white; color: #333333; font-family: arial, helvetica, sans-serif; font-size: xx-small;"> and </span><a href="mailto:powerwaymaterial@gmail.com" style="background-color: white; color: #333333; font-family: arial, helvetica, sans-serif; font-size: small; text-decoration-line: none;">powerwaymaterial@gmail.com</a>wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-88749696581730799372019-11-19T23:28:00.001-08:002019-11-19T23:28:26.722-08:00Annealing Effects on Ge/SiO2 Interface Structure in Wafer-Bonded Germanium-on-Insulator Substrates<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="color: #333333;">We have investigated annealing effects on Ge/SiO</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;"> interfaces in wafer-bonded <b>germanium</b>-on-insulator substrates using transmission electron microscopy and electron energy loss spectroscopy. A number of nanometer-sized hollows were observed at the Ge/SiO</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;"> interfaces after annealing at 500 and 600 °C, while the density of these hollows was very small after annealing at 700 and 800 °C. The hollows are attributed to the formation of amorphous <b>oxides</b> of Si-rich Si</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">1-<i style="border: 0px; font-stretch: inherit; font-variant: inherit; font-weight: inherit; line-height: inherit; margin: 0px; padding: 0px; vertical-align: baseline;">x</i></span><span style="color: #333333;">Ge</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;"><i style="border: 0px; font-stretch: inherit; font-variant: inherit; font-weight: inherit; line-height: inherit; margin: 0px; padding: 0px; vertical-align: baseline;">x</i></span><span style="color: #333333;">O</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;">. The mechanism for the formation and disappearance of these amorphous hollows on the Ge substrates is discussed.</span></span><br />
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<span style="color: #333333; font-family: "arial" , "helvetica" , sans-serif; font-size: x-small;">Source:IOPscience</span><br />
<span style="color: #333333; font-family: "arial" , "helvetica" , sans-serif; font-size: x-small;">For more information, please visit our website: <a href="http://www.semiconductorwafers.net%2C/">www.semiconductorwafers.net,</a></span><br />
<span style="color: #333333; font-family: arial, helvetica, sans-serif; font-size: x-small;">send us email at </span><a href="mailto:sales@powerwaywafer.com" style="color: #333333; font-family: arial, helvetica, sans-serif; font-size: small;">sales@powerwaywafer.com</a><span style="color: #333333; font-family: arial, helvetica, sans-serif; font-size: x-small;"> and </span><a href="mailto:powerwaymaterial@gmail.com" style="color: #333333; font-family: arial, helvetica, sans-serif; font-size: small;">powerwaymaterial@gmail.com</a>wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com1tag:blogger.com,1999:blog-6793036142450899302.post-44463690890117266862019-11-11T01:52:00.001-08:002019-11-11T01:52:38.170-08:00Electrical Characterization of Wafer-Bonded Germanium-on-Insulator Substrates Using a Four-Point-Probe Pseudo-Metal–Oxide–Semiconductor Field-Effect Transistor<span style="color: #333333;"><span style="font-family: Arial, Helvetica, sans-serif;">The electrical characteristics of wafer-bonded non-doped germanium-on-insulator (GOI) substrates were investigated using a four-point-probe pseudo-metal–oxide–semiconductor <b>field-effect transistor.</b> Annealing the wafer-bonded GOI substrates in vacuum strongly influenced their electrical characteristics. GOI samples annealed at temperatures below 500 °C exhibited n-channel depletion transistor operation, whereas GOI samples annealed at temperatures between 550 and 600 °C exhibited p-channel depletion transistor operation. The carrier mobility strongly depended on the sweep direction of the gate voltage; this characteristic disappeared after annealing at temperatures above 550 °C. The dependence of the electrical characteristics on the annealing temperature is explained in terms of the influence of the defect states on energy band bending near the interface.</span></span><br />
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<span style="background-color: white; color: #222222; font-family: "arial" , "helvetica" , sans-serif; font-size: 13.2px;">Source:IOPscience</span><br />
<span style="background-color: white; color: #222222; font-family: "arial" , "helvetica" , sans-serif; font-size: 13.2px;"><span style="color: #444444;">For more information, please visit our website: </span><span lang="EN-US" style="color: #444444;"><v:shapetype coordsize="21600,21600" filled="f" id="_x0000_t75" o:preferrelative="t" o:spt="75" path="m@4@5l@4@11@9@11@9@5xe" stroked="f"><v:stroke joinstyle="miter"><v:formulas><v:f eqn="if lineDrawn pixelLineWidth 0"><v:f eqn="sum @0 1 0"><v:f eqn="sum 0 0 @1"><v:f eqn="prod @2 1 2"><v:f eqn="prod @3 21600 pixelWidth"><v:f eqn="prod @3 21600 pixelHeight"><v:f eqn="sum @0 0 1"><v:f eqn="prod @6 1 2"><v:f eqn="prod @7 21600 pixelWidth"><v:f eqn="sum @8 21600 0"><v:f eqn="prod @7 21600 pixelHeight"><v:f eqn="sum @10 21600 0"></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:formulas><v:path gradientshapeok="t" o:connecttype="rect" o:extrusionok="f"><o:lock aspectratio="t" v:ext="edit"></o:lock></v:path></v:stroke></v:shapetype><v:shape id="图片_x0020_1" o:spid="_x0000_i1025" style="height: 11.25pt; visibility: visible; width: 15pt;" type="#_x0000_t75"><v:imagedata o:title="%W@GJ$ACOF(TYDYECOKVDYB" src="file:///C:\Users\ADMINI~1\AppData\Local\Temp\msohtmlclip1\01\clip_image001.png"></v:imagedata></v:shape></span><span lang="EN-US"><a href="http://www.semiconductorwafers.net/" style="color: #4d469c; text-decoration-line: none;">www.semiconductorwafers.net</a>,</span></span><br />
<span style="background-color: white; color: #222222; font-family: "arial" , "helvetica" , sans-serif; font-size: 13.2px;"><span style="color: #444444;">send us email at <a href="mailto:sales@powerwaywafer.com" style="color: #888888; text-decoration-line: none;">sales<span style="color: #4d469c;">@powerwaywafer.com</span></a> and <a href="mailto:powerwaymaterial@gmail.com" style="color: #4d469c; text-decoration-line: none;">powerwaymaterial@gmail.com</a></span></span><br />
<span style="color: #333333; font-size: 18px;"><span style="font-family: "arial" , "helvetica" , sans-serif;"><br /></span></span>wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-84451062935229213342019-11-06T18:30:00.003-08:002019-11-06T18:30:40.321-08:00Phonon Limited Electron Mobility in Germanium FinFETs: Fin Direction DependenceWe investigate the phonon limited <b>electron mobility</b> in <b>germanium</b> (Ge) fin field-effect transistors (FinFETs) with fin rotating within (001), (110), and (111)-oriented wafers. The coupled Schrödinger–Poisson equations are solved self-consistently to calculate the electronic structures for the two-dimensional electron gas, and Fermi's golden rule is used to calculate the phonon scattering rate. It is concluded that the intra-valley acoustic phonon scattering is the dominant mechanism limiting the electron mobility in Ge FinFETs. The phonon limited electron motilities are influenced by wafer orientation, channel direction, fin thickness W fin, and inversion <b>charge density</b> N inv. With the fixed W fin, fin directions of $\langle 110\rangle $, $\langle 1\bar{1}2\rangle $ and $\langle \bar{1}10\rangle $ within (001), (110), and (111)-oriented wafers provide the maximum values of electron mobility. The optimized Wfin for mobility is also dependent on wafer orientation and channel direction. As Ninv increases, phonon limited mobility degrades, which is attributed to electron repopulation from a higher mobility valley to a lower mobility valley as Ninv increases.<br />
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<span style="background-color: white; font-family: arial, helvetica, sans-serif; font-size: 13.2px;">Source:IOPscience</span><br />
<span style="background-color: white; color: #222222; font-family: arial, helvetica, sans-serif; font-size: 13.2px;"><span style="color: #444444;">For more information, please visit our website: </span><span lang="EN-US" style="color: #444444;"><v:shapetype coordsize="21600,21600" filled="f" id="_x0000_t75" o:preferrelative="t" o:spt="75" path="m@4@5l@4@11@9@11@9@5xe" stroked="f"><v:stroke joinstyle="miter"><v:formulas><v:f eqn="if lineDrawn pixelLineWidth 0"><v:f eqn="sum @0 1 0"><v:f eqn="sum 0 0 @1"><v:f eqn="prod @2 1 2"><v:f eqn="prod @3 21600 pixelWidth"><v:f eqn="prod @3 21600 pixelHeight"><v:f eqn="sum @0 0 1"><v:f eqn="prod @6 1 2"><v:f eqn="prod @7 21600 pixelWidth"><v:f eqn="sum @8 21600 0"><v:f eqn="prod @7 21600 pixelHeight"><v:f eqn="sum @10 21600 0"></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:formulas><v:path gradientshapeok="t" o:connecttype="rect" o:extrusionok="f"><o:lock aspectratio="t" v:ext="edit"></o:lock></v:path></v:stroke></v:shapetype><v:shape id="图片_x0020_1" o:spid="_x0000_i1025" style="height: 11.25pt; visibility: visible; width: 15pt;" type="#_x0000_t75"><v:imagedata o:title="%W@GJ$ACOF(TYDYECOKVDYB" src="file:///C:\Users\ADMINI~1\AppData\Local\Temp\msohtmlclip1\01\clip_image001.png"></v:imagedata></v:shape></span><span lang="EN-US"><a href="http://www.semiconductorwafers.net/" style="color: #4d469c; text-decoration-line: none;">www.semiconductorwafers.net</a>,</span></span><br style="background-color: white; color: #222222; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif; font-size: 13.2px;" /><span style="background-color: white; color: #222222; font-family: arial, helvetica, sans-serif; font-size: 13.2px;"><span style="color: #444444;">send us email at <a href="mailto:sales@powerwaywafer.com" style="color: #888888; text-decoration-line: none;">sales<span style="color: #4d469c;">@powerwaywafer.com</span></a> and <a href="mailto:powerwaymaterial@gmail.com" style="color: #4d469c; text-decoration-line: none;">powerwaymaterial@gmail.com</a></span></span><br />
<br />wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-14240936090379375932019-10-29T01:22:00.003-07:002019-10-29T01:22:47.368-07:00Thin film germanium on silicon created via ion implantation and oxide trapping<span style="font-family: Arial, Helvetica, sans-serif;">We present a novel process for integrating <b>germanium</b> with silicon-on-insulator (SOI) <b>wafers</b>. Germanium is implanted into SOI which is then oxidized, trapping the germanium between the two oxide layers (the grown oxide and the buried oxide). With careful control of the implantation and oxidation conditions this process creates a thin layer (current experiments indicate up to 20-30nm) of almost pure germanium. The layer can be used potentially for fabrication of integrated photo-detectors sensitive to infrared wavelengths, or may serve as a seed for further germanium growth. Results are presented from electron microscopy and Rutherford back-scattering analysis, as well as preliminary modelling using an analytical description of the process.</span><br />
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<span style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;"><span lang="EN-US" style="color: black;">Source:IOPscience</span><br /><span style="background-color: white; color: #222222;"><span style="color: #444444;">send us email at <a href="mailto:sales@powerwaywafer.com" style="color: #888888; text-decoration-line: none;">sales<span style="color: #4d469c;">@powerwaywafer.com</span></a> and <a href="mailto:powerwaymaterial@gmail.com" style="color: #4d469c; text-decoration-line: none;">powerwaymaterial@gmail.com</a></span></span></span></div>
<span style="background-color: white; color: #222222;"><span style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;"><span style="color: #444444;">For more information, please visit our website: </span><span lang="EN-US" style="color: #444444;"><v:shapetype coordsize="21600,21600" filled="f" id="_x0000_t75" o:preferrelative="t" o:spt="75" path="m@4@5l@4@11@9@11@9@5xe" stroked="f"><v:stroke joinstyle="miter"><v:formulas><v:f eqn="if lineDrawn pixelLineWidth 0"><v:f eqn="sum @0 1 0"><v:f eqn="sum 0 0 @1"><v:f eqn="prod @2 1 2"><v:f eqn="prod @3 21600 pixelWidth"><v:f eqn="prod @3 21600 pixelHeight"><v:f eqn="sum @0 0 1"><v:f eqn="prod @6 1 2"><v:f eqn="prod @7 21600 pixelWidth"><v:f eqn="sum @8 21600 0"><v:f eqn="prod @7 21600 pixelHeight"><v:f eqn="sum @10 21600 0"></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:formulas><v:path gradientshapeok="t" o:connecttype="rect" o:extrusionok="f"><o:lock aspectratio="t" v:ext="edit"></o:lock></v:path></v:stroke></v:shapetype><v:shape id="图片_x0020_1" o:spid="_x0000_i1025" style="height: 11.25pt; visibility: visible; width: 15pt;" type="#_x0000_t75"><v:imagedata o:title="%W@GJ$ACOF(TYDYECOKVDYB" src="file:///C:\Users\ADMINI~1\AppData\Local\Temp\msohtmlclip1\01\clip_image001.png"></v:imagedata></v:shape></span><span lang="EN-US"><a href="http://www.semiconductorwafers.net/" style="color: #4d469c; text-decoration-line: none;">www.semiconductorwafers.net</a>,</span></span></span>wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0tag:blogger.com,1999:blog-6793036142450899302.post-27410789701497884102019-08-28T02:09:00.000-07:002019-08-28T02:09:11.482-07:00Breakthrough synthesis method to speed commercialization of graphene<br />
Graphene has one hundred times greater electron mobility than silicon, the most widely used material in semiconductors today. It is more durable than steel and has high heat conductibility as well as flexibility, which makes it the perfect material for use in flexible displays, wearables and other next generation electronic devices.<br />
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<span style="background-color: white; font-family: arial, helvetica, sans-serif;">Source:</span><span style="font-family: arial, helvetica, sans-serif;">phys.org</span><br />
<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="background-color: white; color: #444444;">For more information, please visit our website: </span><span lang="EN-US" style="background-color: white; color: #444444;"><v:shapetype coordsize="21600,21600" filled="f" id="_x0000_t75" o:preferrelative="t" o:spt="75" path="m@4@5l@4@11@9@11@9@5xe" stroked="f"><v:stroke joinstyle="miter"><v:formulas><v:f eqn="if lineDrawn pixelLineWidth 0"><v:f eqn="sum @0 1 0"><v:f eqn="sum 0 0 @1"><v:f eqn="prod @2 1 2"><v:f eqn="prod @3 21600 pixelWidth"><v:f eqn="prod @3 21600 pixelHeight"><v:f eqn="sum @0 0 1"><v:f eqn="prod @6 1 2"><v:f eqn="prod @7 21600 pixelWidth"><v:f eqn="sum @8 21600 0"><v:f eqn="prod @7 21600 pixelHeight"><v:f eqn="sum @10 21600 0"></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:formulas><v:path gradientshapeok="t" o:connecttype="rect" o:extrusionok="f"><o:lock aspectratio="t" v:ext="edit"></o:lock></v:path></v:stroke></v:shapetype><v:shape id="图片_x0020_1" o:spid="_x0000_i1025" style="height: 11.25pt; visibility: visible; width: 15pt;" type="#_x0000_t75"><v:imagedata o:title="%W@GJ$ACOF(TYDYECOKVDYB" src="file:///C:\Users\ADMINI~1\AppData\Local\Temp\msohtmlclip1\01\clip_image001.png"></v:imagedata></v:shape></span><span lang="EN-US" style="background-color: white;"><a href="http://www.semiconductorwafers.net/" style="color: #4d469c;">www.semiconductorwafers.net</a>,</span></span><br />
<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="background-color: white; color: #444444; font-family: "arial" , "helvetica" , sans-serif;">send us email at <a href="mailto:sales@powerwaywafer.com">sales<span style="color: #4d469c;">@powerwaywafer.com</span></a> and <a href="mailto:powerwaymaterial@gmail.com" style="color: #4d469c;">powerwaymaterial@gmail.com</a></span></span>wafer Qualitymaterial_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/10017452612054584096noreply@blogger.com0