Mar 31, 2014

Automatic measurement of thickness as applied to germanium wafer production in transistor manufacture

The paper first examines the problems involved in the measurement of the thickness of germanium wafers, the difficulties encountered in handling and manoeuvring them due to their small size and weight and the nature of their material composition. Errors and failings in hand measurement are discussed, together with the advantages of mechanical measurement. The design and construction of an automatic measuring machine are then described, showing how the wafers are measured, sorted into seven different sizes and counted. The movement of them to the measuring point is by mechanical means, but they are measured, sorted and counted electronically. Measurement is effected by an electronic comparator of high magnification and accuracy, the output signal of which is amplified and then used to operate the sorting mechanism. Some half-million wafers were measured during the development period, which is described, together with the difficulties encountered and the modifications found necessary finally to produce the consistency and accuracy of measurement required. In conclusion, the assets of the machine in eliminating human error in hand measurement and operator fatigue, together with its production capacity, are described.

Source:IEEE

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Mar 25, 2014

Large diameter germanium wafers for CPV applications

Umicore has a long tradition in supplying germanium wafers to the space solar cell market. The main product for this application up to today is a substrate with a diameter of 100 mm and a thickness in the range of 140 – 180 ¼m. With the new emerging market of high-efficiency concentrator photovoltaics (CPV) the need has arisen to investigate the use of germanium wafers with a larger diameter. Especially for small size CPV cells, increasing the wafer diameter will significantly reduce the processing cost per die, which will also contribute to lowering the overall cost/kWh of CPV technology. In this paper the development of dislocation free 150 mm germanium wafers for CPV applications is presented. Different wafer thicknesses down to 200 ¼m have been realized. The process steps starting from crystal pulling up to final epi-cleaning and drying will be addressed. First measurement results on wafer level are shown as well. Finally, the future challenges in optimizing the 150 mm waferspecifications will be reviewed.

Source:IEEE

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Mar 12, 2014

X-ray Diffraction Topography of Germanium Wafers

X-ray diffraction topography in transmission and reflection has been employed to analyze crystal faults and stresses in germanium wafers caused by deposition of oxide layers, epitaxy and planar diffusion. Localized diffusion of arsenic, gallium and phosphorus normally does not introduce stresses sufficiently high to generate dislocations in germanium (011) wafers. However, heat treatment of germaniumwafers covered with a SiO2 film causes high stresses which are often relieved by plastic deformation.

Source:IEEE

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Mar 5, 2014

High performance n+/p and p+/n germanium diodes at low-temperature activation annealing

In this work we demonstrate the fabrication and characterization of high performance junction diodes using annealing temperatures within the temperature range of 300–350 °C. The low temperature dopant activation was assisted by a 50 nm platinum layer which transforms into platinum germanide during annealing. The fabricated diodes exhibited high forward currents, in excess of 400 A/cm2 at ∼|0.7| V for both p+/n and n+/p diodes, with forward to reverse ratio IF/IR greater than 104. Best results for the n+/p junctions were obtained at the lower annealing temperature of 300 °C. These characteristics compare favorably with the results of either conventional or with Ni or Co assisted dopant activation annealing. The low-temperature annealing in combination with the high forward currents at low bias makes this method suitable for high performance/low operating power applications, utilizing thus high mobility germanium substrates.

Source: Microelectronic Engineering

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