Mar 29, 2020

(Invited) Optoelectronic Monolithic Integration of Waveguided Metal-Germanium-Metal Photodetector and Ge CMOSFETs on SOI Wafer

We demonstrate monolithic integration of waveguided Metal- Germanium -Metal photodetector (WG-MGM-PD) and Ge CMOS with high-k dielectric and metal gate on SOI wafer using novel epi-growth technique. WG-MGM-PD achieves a responsivity of 0.6A/W and speed (f3dB) of 17.4GHz. Ge CMOS with ultra-thin EOT (1.4nm) was demonstrated with 2 times hole mobility improvement over the Si universal mobility and very low gate leakage current (10-5~10-4A/cm2).

Source:IOPscience

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Mar 23, 2020

Mesoporous Germanium Formation by Electrochemical Etching

Uniform thick mesoporous germanium layers are reproducibly formed on 4 in. p-type Ge wafers by electrochemical etching in highly concentrated HF electrolytes. Pore formation by anodic etching in germanium leads to a constant dissolution of the porous layer. The growth rate of the porous Ge layer is therefore given by the difference between the etch rate at the porous layer/substrate wafer interface and the dissolution rate at the electrolyte/porous layer interface. The growth rate lies in the range of 0.071–2.7 nm/min for etching current densities of , while both the etch rate and the dissolution rate lie in the range of several micrometers per minute. We define the substrate usage as the ratio of the growth rate and the etch rate. This substrate usage determines the growth efficiency of the porous layer and lies in the range of 0.2–2%. Thus, the substrate wafer is thinned substantially during anodic porous layer formation. Constantly alternating from an anodic to a cathodic bias prevents the thinning of the substrate. The dissolution rate decreases, and the usage increases up to 98%.

Source:IOPscience

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Mar 17, 2020

The Diffused Shot‐melting Technique for Making Germanium and Silicon p‐n Junction Devices

The diffused shot‐melting technique involves the melting and resolidifying of a piece (conveniently obtained in the form of shot) of semiconductor on a wafer of the same material (having essentially the same melting point) to form a single crystal boundary region, and the subsequent diffusion of impurities across the interface. Shot‐melting may be done so quickly that the interface coincides with the original surface of the wafer. Impurity contents of the shot and wafer may be chosen so that a variety of p‐n junction devices results after diffusion, and several junctions may be made on the same wafer by this process to form more complex structures. Although lifetime and resistivity changes generally occur, they can often be minimized by subsequent treatment such as alloy gettering or annealing. Simplicity and flexibility of diffused shot‐melting have made it a convenient laboratory technique for making many semiconductor devices.

Source:IOPscience

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Mar 10, 2020

Resist Stripping Process on Germanium : a Basic Post-Implant Study

Germanium and Germanium-On-Insulator (GeOI) MOSFETs with high-k gate dielectrics have received recent attention for the advanced technology nodes, because of the better carrier transport properties in Ge compared to Si. For Ge or GeOI CMOS, it is mandatory to determine Ge dedicated resist stripping processes, because of the Germanium non-compatibility with actual cleaning solutions. An initial compatibility study shows a passivation effect on germanium during dry step for high N2/ (O2+N2) plasma ratio. For the post active area etching, dry stripping performed on patterned Poly-Ge-On-Insulator (PolyGeOI) wafers shows good compatibility. The lateral Ge consumption due to the water rinse step is minimized by dry process, indicating a plasma passivation effect. Post implant stripping is especially difficult because the Si typical solutions are highly aggressive for Ge, and also because of the resist graphitization. Using a ramping temperature process, a good resist removal efficiency has been achieved.


Source:IOPscience

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Mar 4, 2020

Relationships of the Chemical and Electrical Interfacial Properties of Germanium ‐ SiO2 Systems

Germaniumsilicon dioxide structures were prepared by depositing on cleaned germanium wafers using chemical vapor deposition (CVD) from the silane‐oxygen reaction at 450°C. The structures were then annealed in various gas environments, Ar, , and a  and  forming gas, at 600°C for 2 hr. For samples annealed in forming gas, the interface state density measured by C‐V techniques shows a high density near the band edges (1014/cm2‐eV). For samples annealed in oxygen, it decreases to 1011/cm2‐eV. High surface recombination velocity was observed in the samples annealed in forming gas. The measured results of charge generation and injection indicated charge losses to the interface states but not to oxide traps, whose time constant for trapping is longer than the normal injection time . In order to understand the effects of annealing with different gas environments, profile analyses of the structures were carried out using secondary ion mass spectrometry (SIMS) and Auger electron spectroscopy (AES). For the samples annealed in oxygen, the presence of germanium oxide was identified by observing the low energy Auger spectrum at the interface in comparison with the spectrum obtained for a standard  sample. The profile of the germanium spectrum obtained using SIMS can be used to identify the presence of the oxide because of the enhanced secondary ion yield of the oxide. In the case of the forming gas anneal, the hydrogen appears to diffuse into the interface resulting in a high interface state density. The profile of hydrogen concentration for the structures was also obtained. It is concluded that the increase of the interface state density of a  system due to the forming gas anneal appears to result from dissolved hydrogen diffusing through the . The reduction of interface state density of the structure annealed in oxygen is probably due to the oxidation of germanium and dissolved hydrogen, which reduces the defects originally present in the interface region following the  deposition.

Source:IOPscience

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