Germanium Wafers: May 2018

May 15, 2018

Heterostructures of germanium nanowires and germanium–silicon oxide nanotubes and growth mechanisms

We report on a method to fabricate one-dimensional heterostructures of germanium nanowires (GeNWs) and germanium–silicon oxide nanotubes (GeSiOxNTs). The synthesis of the wire–tube heterostructures is carried out using a simple furnace set-up with germanium tetraiodide and germanium powders as growth precursors, gold-dotted silicon wafers as substrates and by controlling the temperature ramp rate/sequence of the growth precursors. Two types of wire–tube heterostructures resulting from distinct growth mechanisms are obtained. The type-1 heterostructure consists of a GeNW, grown via a gold-catalyzed vapour–liquid–solid process, at the lower end and a GeSiOxNT at the upper end. In contrast, the type-2 heterostructure is made up of a solid wire at the upper end and a hollow tube at the lower end. The solid wire portion of the type-2 heterostructure is formed through an oxide-assisted growth process.

Source:IOPscience

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May 7, 2018

Fabrication of Ge-on-insulator wafers by Smart-CutTM with thermal management for undamaged donor Ge wafers

Newly engineered substrates consisting of semiconductor-on-insulator are gaining much attention as starting materials for the subsequent transfer of semiconductor nanomembranes via selective etching of the insulating layer. Germanium-on-insulator (GeOI) substrates are critically important because of the versatile applications of Ge nanomembranes (Ge NMs) toward electronic and optoelectronic devices. Among various fabrication techniques, the Smart-CutTM technique is more attractive than other methods because a high temperature annealing process can be avoided. Another advantage of Smart-CutTM is the reusability of the donor Ge wafer. However, it is very difficult to realize an undamaged Ge wafer because there exists a large mismatch in the coefficient of thermal expansion among the layers. Although an undamaged donor Ge wafer is a prerequisite for its reuse, research related to this issue has not yet been reported. Here we report the fabrication of 4-inch GeOI substrates using the direct wafer bonding and Smart-CutTM process with a low thermal budget. In addition, a thermo-mechanical simulation of GeOI was performed by COMSOL to analyze induced thermal stress in each layer of GeOI. Crack-free donor Ge wafers were obtained by annealing at 250 °C for 10 h. Raman spectroscopy and x-ray diffraction (XRD) indicated similarly favorable crystalline quality of the Ge layer in GeOI compared to that of bulk Ge. In addition, Ge p-n diodes using transferred Ge NM indicate a clear rectifying behavior with an on and off current ratio of 500 at ±1 V. This demonstration offers great promise for high performance transferrable Ge NM-based device applications.