Resist Stripping Process on Germanium : a Basic Post-Implant Study
Germanium and Germanium-On-Insulator (GeOI) MOSFETs with high-k gate dielectrics have received recent attention for the advanced technology nodes, because of the better carrier transport properties in Ge compared to Si. For Ge or GeOI CMOS, it is mandatory to determine Ge dedicated resist stripping processes, because of the Germanium non-compatibility with actual cleaning solutions. An initial compatibility study shows a passivation effect on germanium during dry step for high N2/ (O2+N2) plasma ratio. For the post active area etching, dry stripping performed on patterned Poly-Ge-On-Insulator (PolyGeOI) wafers shows good compatibility. The lateral Ge consumption due to the water rinse step is minimized by dry process, indicating a plasma passivation effect. Post implant stripping is especially difficult because the Si typical solutions are highly aggressive for Ge, and also because of the resist graphitization. Using a ramping temperature process, a good resist removal efficiency has been achieved.
No comments:
Post a Comment